Deep-submicron scaling required for ULSI Systems dominates design considerations in the micro electronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly, to suppress the so-called short channel effects (SCE) which degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth (X.sub.j) and polycrystalline silicon line width are scaled into the deep-submicron range, parasitic series resistances of the source/drain diffusion layers and polysilicon gate electrodes increase. A conventional approach to the increase in parasitic series resistances of the source/drain diffusion layers and the polysilicon gate electrodes involves salicide technology which comprises forming a layer of titanium silicide (TiSi.sub.2) on the source/drain regions and gate electrode.
Conventional salicide technology employing TiSi.sub.2 for reducing parasitic series resistance has proven problematic, particularly as design rules plunge into the deep-submicron range, e.g., about 0.18 microns and under. For example, in forming a thin TiSi.sub.2 layer, silicide agglomeration occurs during silicide annealing to effect a phase change from the high resistivity C49 form to the low resistivity C54 form. Such agglomeration further increases the sheet resistance of the silicide film. Moreover, the formation of a thick silicide layer causes a high junction leakage current and low reliability, particularly when forming ultra shallow junctions, e.g., at an X.sub.j of less than about 800 .ANG.. The formation of a thick silicide layer consumes silicon from the underlying semiconductor substrate such that the thick silicide layer approaches and even shorts the ultra-shallow junction, thereby generating a high junction leakage current.
Another problem attendant upon conventional TiSi.sub.2 technology is the well-known increase in sheet resistance as the line width narrows. The parasitic series resistances of source/drain regions and gate electrodes are a major cause of device performance degradation and are emerging as one of the severest impediments to device scaling.
There are additional problems attendant upon conventional silicide technology employing titanium or other metals, such as cobalt, which problems are exacerbated as design rules extend into the deep-submicron range, e.g. about 0.18 microns and under. For example, conventional salicide technology for deep-submicron CMOS transistors comprises depositing a layer of metal at a predetermined thickness by physical vapor deposition (PVD), such as sputtering, over the entire wafer surface and then conducting a two step rapid thermal annealing with an intervening etching step to remove unreacted metal from the dielectric sidewall spacers on the gate electrode as well as the field isolation region. The need to remove unreacted metal from the dielectric sidewall spacers and field isolation region complicates processing and reduces manufacturing throughput as well as device reliability. In addition, as devices are scaled smaller and smaller, shorting between source/drain regions and the gate electrode becomes significant due to high temperature processing required to form low resistivity silicide layers.
There exist a need for simplified salicide technology which enables a reduction in parasitic series resistances. There exist a particular need for simplified salicide methodology in manufacturing semiconductor devices having a design rule in the deep-submicron range, e.g. a design rule less than about 0.18 microns, with increased reliability and reduced shorting between source/drain regions and the gate electrode.